Products

S5PE-DS
s5peds-MAIN
Main Features
  • - Two high-density Altera Stratix V GX/GS FPGAs
  • - PCIe x16 interface supporting Gen1, Gen2, or Gen3
  • - Four QSFP+ cages for 4 40GigE, 16 10GigE, or 4 QDR/FDR InfiniBand direct to the FPGAs
  • - Eight SATA connectors, up to 6 Gbps each
  • - Timestamping support
  • - Baseboard Management Controller for Intelligent Platform Management
  • - Utility I/O includes: USB 2.0, RS-232, and JTAG
  • - Memory:up to 64 GBytes of DDR3 SDRAM with ECC

Dual Altera Stratix® V GX/GS PCIe Board with Quad QSFP+, DDR3, QDRII+, and RLDRAM3

S5-PCIe-DS (S5PE-DS) is a PCIe x16 card featuring two high-bandwidth, power-efficient Altera Stratix V GX or GS FPGAs. Designed for high-end applications, the Stratix V provides a high level of system integration and flexibility for I/O, routing, and processing. The S5PE-DS provides up to 64 GBytes of DDR3 SDRAM as well as options for RLDRAM3 and QDRII+. Providing additional flexibility are four front-panel QSFP cages, allowing 4 40GigE interfaces, 16 10GigE, or 4 QDR/FDR InfiniBand interfaces direct to the FPGAs’ built in PHYs for the lowest possible latency. With almost 2 million logic elements available (952,000 per FPGA), the board is ideal for high-performance computing, and with the reduced latency provided by the network interfaces, ideal for high frequency trading, military/government agency secure communications, and network processing applications. 

FPGAs

  • 2 Altera® Stratix® V GX/GS FPGAs
  • 28 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 14.1 Gbps (per FPGA)
  • Up to 952,000 logic elements (LEs) per FPGA
  • Up to 62 Mb of embedded memory per FPGA
  • 1.4 Gbps LVDS performance
  • Up to 3,926 18×18 variable-precision multipliers per FPGA
  • Embedded HardCopy Blocks

Memory

  • 4 SODIMM sites per FPGA: DDR3 SDRAM, RLDRAM3, or QDRII+ options
  • 256 MBytes of Flash memory for booting FPGA

PCIe Interface

  • PLX PEX8733 PCIe switch with on-chip DMA engines
  • x16 Gen1, Gen2, Gen3 to host
  • x8 Gen 1, Gen2, Gen 3 to each FPGA

USB Header

  • USB 2.0 interface for debug and programming FPGAs and Flash

Timestamp Header

  • 1 PPS input
  • Reference clock input
  • RS-232

Debug Utility Header

  • RS-232 port to Stratix V
  • JTAG debug interface to Stratix V

QSFP+ Cages

  • 4 QSFP+ cages on front panel connected directly to FPGAs via 16 SerDes (no external PHY)
  • Each QSFP+ supports 40GigE, 4 10GigE, or QDR/FDR InfiniBand interfaces

Serial ATA

  • 8 SATA connectors, connected to FPGAs

Baseboard Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Size

  • Full-length, standard-height, dual-slot PCIe x16 card

Optional SODIMMs 4 for FPGA can be any of the follow:

DDR3: x72 w/ECC

  • Up to 8 GB per SODIMM

RLDRAM3: 2x banks of x18

  • 2x (64 M x 18): 256 MB per SODIMM
  • 2x (128M x 18): 512 MB per SODIMM

QDRII+: 2x banks of x18

  • 36 MB (2 x 18) per SODIMM

Development Tools

System Development

  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; source code porting kit also available

FPGA Development Kit

  • Physical interface components
  • Board, I/O, and timing constraints
  • Example Quartus projects
  • Software components and drivers

FPGA Development

  • Altera Quartus® II software

Accessory Boards

  • BittWare BWBO breakout board for debug
Datasheet

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